1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Semiconductor On Insulator) structure and a manufacturing method thereof, and more particularly, it is concerned with a semiconductor device having an SOI structure in which elements are isolated from each other by using a field shield gate and a manufacturing method of such a semiconductor device.
2. Description of the Background Art
Conventionally, a field shield (hereinafter referred merely to as "FS") isolation has been known as a method for isolating elements electrically from each other. A semiconductor memory device utilizing the conventional FS isolation will be described below.
FIG. 69 is a cross sectional view showing a conventional semiconductor device formed on a bulk silicon substrate wherein elements are isolated by the FS isolation. The use of an FS gate for isolation of transistors on the bulk silicon substrate has been proposed in several reports including IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-19, No. 11, November, 1972, pp. 1199-pp. 1206 by H. C. Lin et al.
With reference to FIG. 69, an n well region 104 and a p well region 105 are respectively formed on a main surface of a p type silicon substrate 101. An nMOS 102 is formed on the surface of p well region 105. A pMOS 103 is formed on the surface of n well region 104. A CMOS is formed by pMOS 103 and nMOS 102 which are isolated from each other by an FS gate 116.
nMOS 102 includes an n.sup.- diffusion region 107, an n.sup.+ diffusion region 108, a gate oxide film 111, and a gate electrode 112. Gate electrode 112 is formed by polycrystalline silicon which includes phosphorus (P) of at least 1.times.10.sup.20 /cm.sup.3. A tungsten silicide (WSi.sub.2) layer 113 is formed on gate electrode 112 so as to reduce resistance of gate electrode 112.
pMOS 103 includes a p.sup.31 diffusion region 109, a p.sup.+ diffusion region 110, gate oxide film 111, and gate electrode 112. FS gate 116 is formed on an element isolation region with an FS gate oxide film 115 interposed therebetween.
A silicide layer 114 is formed on the surfaces of n.sup.+ diffusion region 108 and p.sup.+ diffusion region 110 so as to reduce resistance of these diffusion regions 108 and 110. A silicon oxide film 117 is formed to cover gate electrode 112 and FS gate 116. An interlayer oxide film 118 is formed to cover silicon oxide film 117. A contact hole 119 is formed at a predetermined position in interlayer oxide film 118. An interconnection layer 120 mainly made of aluminum (Al) is formed in contact hole 119.
Now, a manufacturing method of a semiconductor device shown in FIG. 69 will be described by using FIGS. 70-82. FIGS. 70-82 show cross sections of first through thirteenth steps of a manufacturing process of the semiconductor device shown in FIG. 69.
With reference to FIG. 70, silicon oxide film 115 having a thickness of about 1000 .ANG. is formed by a CVD (Chemical Vapor Deposition) method on the main surface of p type silicon substrate 101. Polycrystalline silicon layer 116 having a thickness of about 2000 .ANG. is formed on silicon oxide film 115 by CVD. At this time, phosphorus (P) is introduced into polycrystalline silicon layer 116 at a high concentration of about 1.times.10.sup.20 /cm.sup.3. A silicon oxide film 117a having a thickness of about 2000 .ANG. is formed by CVD on polycrystalline silicon layer 116. A resist pattern 121 which is patterned into a predetermined shape is formed on silicon oxide film 117a. Using resist pattern 121 as a mask, silicon oxide film 117a, polycrystalline silicon layer 116, and silicon oxide film 115 are successively etched, whereby FS gate 116 and FS gate oxide film 115 are formed. Then, resist pattern 121 is removed.
With reference to FIG. 71, silicon oxide film 117b having a thickness of about 2000 .ANG. is formed by CVD on the entire main surface of p type silicon substrate 101. Silicon oxide film 117b is subjected to etching in an ambience of gas having a high anisotropic characteristic, whereby silicon oxide film 117 covering FS gate 116 is formed as shown in FIG. 72.
With reference to FIG. 73, resist patten 121 is formed on the main surface of p type silicon substrate 101 so as to cover only a pMOS formation region. Using resist pattern 121 as a mask, boron (B) ions are implanted onto the main surface of p type silicon substrate 101. The ion implantation is conducted in three steps based on the following three kinds of conditions. Conditions are: 1-2.times.10.sup.13 /cm.sup.2 at 700 keV; 2-4.times.10.sup.12 /cm.sup.2 at 160 keV; and 1-2.times.10.sup.13 /cm.sup.2 at 50 keV. Through such three steps of ion implantation, p well region 105 is formed.
With reference to FIG. 74, resist pattern 121 is formed on the main surface of p type silicon substrate 101 so as to cover only an nMOS formation region. Using resist pattern 121 as a mask, phosphorus (P) ions are implanted onto the main surface of p type silicon substrate 101. Ion implantation is also conducted in three steps in this case. Conditions are: 1-2.times.10.sup.13 /cm.sup.2 at 1200 keV; 2-4.times.10.sup.12 /cm.sup.2 at 400 keV; and 1-2.times.10.sup.13 /cm.sup.2 at 180 keV. Then, boron (B) ions are implanted at 20 keV for 2-3.times.10.sup.13 /cm.sup.2, whereby n well region 104 is formed.
As described above, in order to form a transistor on the bulk silicon substrate, it is necessary to conduct ion implantation in several steps with implantation energy or implantation concentration changed. The reasons for this include prevention of punch-through in a short channel region (a gate length of 0.5 .mu.m or less), suppression of the change of transistor characteristics caused by variation of the substrate bias, and avoidance of deterioration of the device characteristics (soft error) caused by charge generated by radiation such as an .alpha.-line injected from the external ambience. Therefore, the above-described complex well formation is required for forming the transistor on the bulk silicon substrate.
Now, with reference to FIG. 75, the channel region surfaces of pMOS 103 and nMOS 102 are subjected to wet etching by using a solvent including aqueous ammonia (NH.sub.4 OH), hydrofluoric acid (HF) and hydrogen chloride (HCl), thus removing a foreign object or natural oxide film provided on the channel region surface. Then, gate oxide film 111 is formed by thermal oxidation or the like to have a thickness of, preferably, about 80-100 .ANG.. The thickness of gate oxide film 111 is determined to conform to a desired transistor characteristic. Gate oxide film 111 is formed by oxidation at temperatures of 800.degree. C.-950.degree. C.
Polycrystalline silicon layer 112 including phosphorus (P) at a high concentration (1.times.10.sup.20 /cm.sup.3) is formed by CVD on gate oxide film 111. WSi.sub.2 layer 113 is formed by sputtering on polycrystalline silicon layer 112 to have a thickness of, preferably, about 1000 .ANG.. Then, a silicon oxide film 117c having a thickness of about 1000 .ANG. is formed by CVD or the like on WSi.sub.2 layer 113. Resist pattern 121 patterned into a predetermined shape is formed on silicon oxide film 117c. Using resist pattern 121 as a mask, silicon oxide film 117c is etched. Then, resist pattern 121 is removed. Using silicon oxide film 117c as a mask, WSi.sub.2 layer 113 and polycrystalline silicon layer 112 are patterned.
With reference to FIG. 76, resist pattern 121 is formed to cover only the pMOS formation region. Using resist pattern 121 as a mask, phosphorus (P) ions are implanted by continuous rotation at an angle of 45.degree. with 70 keV to attain 1-2.times.10.sup.13 /cm.sup.2 whereby n.sup.+ diffusion region 107 is formed. Then, resist pattern 121 is removed.
With reference to FIG. 77, resist pattern 121 is formed to cover only the nMOS formation region. Using resist pattern 121 as a mask, boron (B) ions are implanted at 10 keV to attain 1-2.times.10.sup.11 /cm.sup.2, whereby p.sup.- diffusion region 109 is formed.
With reference to FIG. 78, a silicon oxide film 117d having a thickness of about 1000-2000 .ANG. is formed by CVD on the entire main surface of p type silicon substrate 101. Silicon oxide film 117d is subjected to etching in an ambience of gas of a high anisotropic characteristic, whereby silicon oxide film 117 is formed to cover gate electrode 112, as shown in FIG. 79. Then, a Ti layer 122 having a thickness of about 500-800 .ANG. is formed by sputtering. At this time, sputter etching is conducted before formation of Ti layer 122 in order to remove the natural oxide film or foreign objects provided on the surface of p type silicon substrate 101.
With reference to FIG. 80, resist pattern 121 is formed to cover only the pMOS formation region. Using resist pattern 121 as a mask, arsenic (As) ions are implanted at 50 keV to attain 4-6.times.10.sup.15 /cm.sup.2 and phosphorus (P) ions are implanted by continuous rotation at 60.degree. with 100 keV to attain 1-2.times.10.sup.14 /cm.sup.2 onto the main surface of p type silicon substrate 101, whereby n.sup.+ diffusion region 108 is formed. Then, resist pattern 121 is removed.
With reference to FIG. 81, resist pattern 121 is formed to cover only the nMOS formation region. Using resist pattern 121 as a mask, BF.sub.2 ions are implanted at 40 keV to attain 4-6.times.10.sup.15 /cm.sup.2 onto the main surface of p type silicon substrate 101, whereby a p.sup.+ diffusion region 110 is formed. Then, resist pattern 121 is removed.
With reference to FIG. 82, interlayer oxide film 118 having a thickness of about 5000-10000 .ANG. is formed by CVD or the like on the main surface of p type silicon substrate 101. Resist pattern 121 patterned into a predetermined shape is formed on interlayer oxide film 118. Using resist pattern 121 as a mask, interlayer oxide film 118 is etched, whereby contact hole 119 shown in FIG. 69 is formed. By sputtering or the like, interconnection layer 120 is formed in contact hole 119 and on interlayer oxide film 118, thus patterning interconnection layer 120 into a predetermined shape. Through above steps is provided the semiconductor device shown in FIG. 69.
FIG. 83 shows an interconnection layer 120a connected to a power supply Vcc terminal being formed at a predetermined position between FS gates 116 in the semiconductor device shown in FIG. 69. As can be seen from FIG. 83, n well region 104 is usually formed between nMOS 102 and pMOS 103 as shown in FIG. 83. The reason for this is to fix p well region 105 to a ground potential and to fix n well region 104 to a power supply Vcc potential in the case of using p type silicon substrate 101. More particularly, this is because a Vcc terminal is formed on the top surface of p type silicon substrate 101 and a ground terminal is formed on the back surface thereof for the sake of structure of the circuit.
However, there are three disadvantages in isolation of nMOS 102 and pMOS 103 formed on the bulk silicon substrate by FS gate 116, as follows.
The first disadvantage is latch up between nMOS 102 and pMOS 103. One method to avoid such latchup is to increase concentrations of n well region 104 and p well region 105. However, concentrations of n well region 104 and p well region 105 cannot be increased freely because those concentrations are determined for the sake of setup of threshold voltages in nMOS 102 and pMOS 103.
The second disadvantage is a complex formation process of n well region 104 and p well region 105. As described above, several steps are required in ion implantation for forming n well region 104 and p well region 105, thus causing a complex manufacturing process.
The third disadvantage is regarding an isolation capability. A high threshold voltage is desired for the transistor including FS gate 116 in the FS gate isolation. Accordingly, the isolation capability is improved. One method for this is to increase the concentration of p well region 105 or n well region 104 located directly under FS gate 116, or to increase the thickness of FS gate oxide film 115. Increasing the concentration of the region located directly under FS gate 116 can provide an advantage. More particularly, since excessive carriers generated by impact ionization are diffused and collected by a substrate potential fixing terminal (not shown), resistance of a diffusion path of carriers can be reduced. In other words, collection of excessive carries can be conducted effectively.
However, as described above, the concentration of p well region 105 or n well region 104 cannot be increased freely because it is determined for the sake of the threshold voltages of pMOS 103 and nMOS 102. Therefore, the method for increasing the thickness of FS gate oxide film 115 has been adapted commonly to incur a problem of increase of a stepped portion. Thus, in the conventional example, increase of the threshold voltage of the transistor including the FS gate has been difficult. In other words, improvement of the isolation capability has been difficult.
One conceivable method to solve the above-described problems is to use an SOI substrate instead of the bulk silicon substrate. The SOI substrate represents a substrate having an SOI (Semiconductor On Insulator) structure, and includes a substrate, an insulating layer formed on the surface of the substrate, and a thin film silicon layer (hereinafter referred merely to as "SOI layer") formed on the insulating layer.
At the SOI layer in the above-described SOI substrate are provided various circuit elements. In general, a LOCOS method has been conventionally used to isolate circuit elements from each other formed on the SOI substrate. Since each element isolated by this isolating method (LOCOS isolation) is formed on the semiconductor layer having a complete island shape, the problem of latchup is eliminated. Also, this eliminates the complex well formation process, unlike the case of using the bulk silicon substrate. Further, the isolation capability is sufficient.
FIG. 84 is a cross sectional view showing a semiconductor device formed on a conventional SOI substrate. With reference to FIG. 84, a buried oxide film 130 is formed on the main surface of silicon substrate 101. An SOI layer 131 is formed on buried oxide film 130. An isolation oxide film 132 is formed at a predetermined position (element isolation region) of SOI layer 131. nMOS 102 and pMOS 103 are respectively formed within an island-shaped region surrounded by isolation oxide film 132. A p.sup.+ region 133 is formed on nMOS 102 side at the end of isolation oxide film 132, whereby generation of a parasitic MOS can be suppressed. It is noted that in FIG. 84 portions corresponding to components of the semiconductor device shown in FIG. 83 are designated by the same reference numerals and the description thereof will not be repeated.
The following disadvantage is included in nMOS 102 or pMOS 103 completely isolated by the above-described isolation oxide film 132. More particularly, such a complete isolation causes carriers generated by impact ionization to be stored in the channel region of nMOS 102 or pMOS 103 to incur rising of a channel potential. This causes a parasitic bipolar operation, thus reducing a source-drain breakdown voltage of nMOS 102 or pMOS 103. The source/drain breakdown voltage decreases gradually as the gate length is shortened, as shown in FIG. 21 (the LOCOS isolation in FIG. 21). Note that FIG. 21 is a graph showing a relationship between the source/drain breakdown voltage and the gate length.
In order to solve such a problem, the following improvement has been proposed. FIG. 85 is a plan view showing an nMOS portion in an improved example. FIG. 86 is a cross sectional view along line A--A of FIG. 85, and FIG. 85 is a cross sectional view along line C--C of FIG. 85.
First, with reference to FIGS. 85 and 86, an n.sup.- diffusion region 107 and an n.sup.+ diffusion region 108 are respectively formed to define a channel region 140 at an SOI layer 131 enclosed by an isolation oxide film 132. A gate electrode 112 is formed on channel region 140 with gate oxide film 111 interposed therebetween. A silicide layer 114 is formed on the surface of n.sup.+ diffusion region 108. A silicon oxide film 117 is formed to cover gate electrode 112, and an interlayer oxide film 118 is formed to cover silicon oxide film 117. Contact holes 134 and 135 are respectively formed in interlayer oxide film 118, and an interconnection 120 is formed in contact holes 134 and 135.
Next, with reference to FIGS. 85 and 87, a p region 138 formed continuously with channel region 140 and including a p type impurity at the same concentration as that included in channel region 140, and a p.sup.+ region 139 are respectively formed in SOI layer 131. A contact hole 137 is formed in interlayer oxide film 118 located on p.sup.+ region 139. Interconnection layer 120 is formed in contact hole 137 to serve to fix a potential of SOI layer 131.
Excessive carriers stored in channel region 140 by impact ionization reaches to p.sup.+ region 139 through p region 138, and are drawn out by interconnection layer 120 formed in contact hole 137. Thus, rising of the channel potential and the parasitic bipolar operation can be restrained.
However, the following problem occurs even in the above-described improvement. With reference to FIGS. 85 and 87, p region 138 through which the excessive carriers are passed is located under gate electrode 112. This causes depletion of p region 138 as well as channel region 140 in the case when a high voltage is applied to gate electrode 112, whereby movement of the excessive carriers is prevented. In other words, in the above improvement, an efficiency of drawing out the excessive carriers is significantly reduced when the high voltage is applied to gate electrode 112.